|Project NANOLITH (IST 1999
The overall objective of the three years Nanolith project is to demonstrate that parallel e-beam Lithography using an array of electron microguns driven by an active matrix can comply with the future requirements of lithographic mask fabrication, that is a high resolution (10 nm range), high throughput (writing time < 30 min due to parallel writing) and low cost technology (the writing head is fully integrated on a single silicon wafer). Nanolith will demonstrate parallel 100 nm lithography with a matrix of 33 x 33 microguns, each delivering 10 pA, and independently driven with integrated dose control circuits. Each microgun is composed of an electron planar source, made-up in a low electron affinity carbon-based film with artificially engineered emission sites, an extracting lens and a focusing lens. Moreover, microguns with sub 10 nm electron planar sources delivering sub 30 nm beam sizes and suitable for integration in an active matrix will be demonstrated.
Description of the work
During the project, we will study the three critical aspects of the Nanolith concept: high throughput parallel writing with an array of microguns, 10 nm range resolution capability and 100% efficiency of the writing head with integrated circuits and dose control elements. One can note that this corresponds to the three following deliverables : the simulation and circuit design of the 100% efficient writing head concept (D11 at month 24), sub 30 nm size electron beams (D14 at month 36), 100 nm resist structures realised by exposure with an active array of microguns (D15 at month 36). In order to reach these objectives, the work is divided into the following seven workpackages : Electron planar source (EPS) fabrication (WP1), Fabrication and emission properties of planar cathodes (WP2), Fabrication and emission properties of optimised microguns (WP3), Parallel lithography with ~1000 microguns (WP4), Assessment and evaluation (WP5), Dissemination and Use Plan and Technological Implementation Plan (WP6), Project management (WP7). WP1 which corresponds to the EPS fabrication is dedicated to the deposition of carbon material and to the artificial engineering of emission sites in order to determine the best EPS fabrication method. The goal of WP2 is to optimise the structure of planar cathodes using 10-100nm EPSs. It will lead to the complete study of the emission properties of the planar cathodes and to their fabrication yield. WP3 corresponds to the study of optimised microguns for parallel lithography and also for the determination of the ultimate resolution. WP4 is dedicated to parallel 100 nm lithography with an active matrix of microguns. This workpackage includes the lithographic environment requirements, active matrix design (100% efficient writing head concept) and fabrication and 100 nm parallel lithography. The goal of WP7 is to warrant a good and efficient progress of the project and to ensure a complete exploitation of the results.
Milestones and expected results
The Nanolith project includes 9 milestones. The major ones are : determination of the optimised fabrication method for planar cathodes (M2, month 18), characteristics of optimised microguns for 100 nm lithography (M3, month 24), determination of the ultimate resolution with the Nanolith concept (M4, month 36), high throughput capabilities of the Nanolith concept (M6, month 36), Final assessment review including the technological implementation plan (M9, month 36).
The primary objective of this project is to develop self-assembly
technologies for the bottom-up fabrication of nanoscale electronic devices
using assembly strategies learned from Nature. During the project we shall:
develop new materials for the fabrication of nanoparticle-based functional
units; develop protocols for positioning the functional units; develop
templating protocols to enable directed self-assembly of the functional
units into superlattice arrays at technologically relevant interfaces;
develop self-assembly technologies for interconnecting the functional units
(nano-nano) and connecting them to micron scale electrodes (nano-micro
interconnects); demonstrate the fabrication techniques by self-assembly
of single-particle and double-particle devices, and self-assembly of interconnections
in a nanoparticle array; investigate interaction rules between functional
units in these prototypical cellular automata circuit components.
Description of the work
We propose to use a cross-disciplinary approach between biotechnology, materials science, and microelectronics that will result in a set of fabrication tools for the self-assembly of a variety of nanoscale electronic structures, devices, and circuits. These tools will include novel surface-modified semiconductor and metal nanoparticles (NPs) as functional units, bacterial S-layer proteins as templates for superlattice arrays, and novel concepts for nanoscale interconnects. Besides the management, evaluation, and dissemination workpackages, the work plan is divided into 8 main workpackages, each being co-ordinated by one consortium participant. WP2 focuses on NP synthesis, including novel core-shell semiconductor NPs and asymmetrically substituted NPs. WP3 involves biomolecule synthesis to provide the components needed for self-assembly of functional units and interconnects via molecular recognition. WP4 is devoted to the self-assembly of nano-nano and nano-micro interconnects between NPs and metal microcontacts. WP5 performs the directed self-assembly of single and coupled NPs. WP6 provides NP arrays templated by native and genetically modified S-protein monolayers, with subsequent stabilisation in chemically inert matrices. WP7 is responsible for the assembly of interconnects within the S-layer templated NP arrays. WP8 is devoted to device integration and characterisation. Its task involves the design and fabrication of "smart" electrical test structures and the characterisation (electrical/structural/simulation) of NP-based devices, assisted by calculation of electronic and transport properties of inter-particle molecular recognition linkers. During WP9 (Year 3), the developed technologies for self-assembly of demonstrator devices will be optimised with respect to potential room temperature device operation.
Milestones and expected results (maximum 500 characters)
Three demonstrators will be self-assembled: single nanoparticle (NP) devices on µ-patterned Si exhibiting resonant tunnelling (NP-RTD) or single electron charging (NP-SET) with self-assembled nano-micro interconnects; two closely spaced, independently connected NP-RTDs or NP-SETs on a µ-patterned Si wafer as a prototype cellular automata unit to study device interactions; and assembly of interconnections in a NP array.
Project CHANIL (IST-1999-13415)
The objectives of the project are: i) to develop and ii) assess the potential for nanoimprint technology for the coming semiconductor fabrication requirements in the sub-10 nm domain. This willl be realized by exploring i) NIL for making individual structures on the sub-10 nm level as well as exploring ii) the possibility for making imprint over large areas (up to 6" wafers).
The impact of nanoimprint technology, if succesfully transferred to industry, would be huge. Application areas would include e.g. storage technologies (optical, magnetical etc), micro/nano-electronics and bio-sensor devices and would make stong impact onto every-day life.
Description of the work
Nanoimprint lithography (NIL) has the potential to revolutionize the production of nm-scale devices and integrated circuits. Future high volume data storage and high speed data processing will require reliable large area patterning technologies for fabrication of nano-scaled structures. Present lithography for sub-100 nm structures (e-beam, X-ray, ion projection) suffers from severe drawbacks for volume production, limited throughput or expensive equipment.using the same tools developed for the large area sub-100 nm NIL.
This workprogramme is a direct continuation of NANOTECH. It has combined aims of:
As a result we expect a nanofabrication technique with capabilities for mass production aiming towards the sub-10 nm domain, with a clear identification of its potential. Furthermore, nano-imprint technology will be an important contribution to ensure a strong competitive position for the EU in the key emerging technologies for information processing circuits.
Project CORTEX (IST-1999-10236)
The long-term objective is to develop an enabling technology for three-dimensional computer structures, whether micro-, nano-, or molecular-electronic. The specific objective is to demonstrate the feasibility of very high-density, three-dimensional molecular 'wires' between closely-space chips or other types of layer. The technical objectives are:
1. to develop four different 3D molecular connection technologies
2. to measure and compare their performance using the same test structures
3. to investigate the long-term reliability of such connections
4. to investigate closely-spaced through-chip connections and thinning of circuit substrates
5. to determine the maximum number of devices per unit volume
6. to devise computer structures using this new 3D connection technique
Description of the work
We propose a three-year programme to examine the feasibility of connecting two or more closely-spaced semiconductor layers with intercalated molecular wiring layers. Four types of molecular wire technology will be developed by three separate groups. In order to provide a common testing standard, the same type of test rig and 'test chips' will be used to measure conductivity and other electrical properties as a function of the alignment and spacing between the semiconductor layers. There will be five work packages:
WP1 MOLECULAR WIRES: Design, construction and testing of molecular wires.
WP2 TEST CHIPS: Design and construction of silicon test chips and silicon, quartz or glass top-layer assemblies.
WP3 TEST RIG: Design and construction of test rigs.
WP4 ELECTRONIC LAYER FABRICATION: Investigation of factors relating to chip fabrication (wafer thinning methods, high-density through-chip connections, chemical compatibility between semiconductor and molecular elements).
WP5 THREE-D STRUCTURES: How to assemble a layered structure; fault-tolerant structures; low-power architectures.
Milestones and expected results
M1. Test rigs and first test chips made (month 6).
M2. First molecular conductivity measurements under way (m. 9).
M3. First molecular conductivity measurements completed (m. 15).
M4. Second test chips made (m. 18).
M5. Second measurements completed (m. 24).
M6. Third test chips completed (m 30).
M7. Third measurements completed (m. 33).
Development of tools and techniques for the fabrication of electronic devices with critical dimensions below 5 nm and integration of such structures to form logic elements and memory cells. The first phase of the project will emphasise on fundamental investigations. Design and synthesis of a number of tailor-made conducting molecules, using concepts and techniques originating from organic chemistry and supramolecular engineering, combined with surface patterning and nano-manipulation techniques. Chemically synthesised metallic clusters and conjugated molecules will be used to make self-assembled three terminal devices. The second phase will address issues like the interconnections problem and focus on making useful devices with respect to lifetime and reproducibility. New architectures for information processing will be considered, which can be used for implementation of logic devices at the end of the project period.
Description of the work
The project will be divided in two phases in which the first phase emphasise on technology development and fundamental understanding of self-assembly and electron transport in molecular-scale systems. The second phase will focus on making small scale integration and demonstration of devices for information processing, such as logic gates and memory cells. The partners of this collaboration have the competence and skills of synthetic chemistry, lithographic process technology, theory, manipulation of nano-scale objects, measurement techniques and different methods for analysis, which together will have a very strong synergetic effect and assure a successful development of the project. We have identified three directions for the first phase:
1. Definition and realisation of a family of suitable conjugated molecules and investigation of their self- assembling properties
2. Electrical transport measurements of these molecules.
3. Investigation of self-assembly of nanoclusters, with molecular bridging between the clusters.
The strategy will be an iterative process to design, synthesise, characterise and make semi-empirical models which can be used for the design of new molecules with improved performance. The second phase will aim at the development of new architectures built on three terminal devices and the development of more complex molecules, in particular bearing more than two connecting sites, using the verified theoretical models and the same strategy as in phase one. To reach the objectives, the work will be divided in 7 technical workpackages which are interrelated: Synthesis of molecules; synthesis of clusters; and Self-assembly of molecules; Self-assembly of clusters; Transport measurement; Electrode fabrication ; Theory.
Milestones and expected results
A family of conjugated molecules synthesised and characterised.
Models for conductance in molecular wires verified by charge transport measurements.
Analysis of self-assembly processes. Control of a single nanoclusters position between two electrodes.
Model and synthesis of molecules optimised for a three-terminal device.
Fabrication and characterisation of 3-terminal devices made by self-assembly of nanoobjects.
The desired characteristics of a memory cell for computer main memory are high speed, low power consumption and dissipation, non-volatility, high packing density and low cost. The overall thrust of NanoMEM is to develop two new varieties of Tunnelling-MRAM (Magnetic Random Access Memory) based on two terminal device MIMRAM (Metal- Insulator-Metal RAM) and three terminal device TTRAM (Tunnelling Transistor RAM). The objective of this proposal is to develop this new technology to the degree where it is capable to replace the currently available generation of RAM (which is based on semiconductor technology) in all applications. In the longer term, the basic science of this project also paves the way for replacing computer hard disks with Tunnelling-MRAMs, thus affording much faster memory access times and no moving parts. Compared with other Tunnelling-MRAM architectures, the MIMRAM and TTRAM offer the advantage of small cell size and hence high packing density, in conjunction with suppression of parasitic signal paths in read and write operations. This will allow in a first step the length-scale of MRAM cells to be reduced from 0.35 microns to 100 nanometers and possibly below.
The principal milestones and expected results are:
The project will be carried out in three phases, which are organised into six workpackages (WP1-WP6). Phase 1 explores the properties of a single cell inside MRAM arrays. This will be addressed within WP1 (Magnetic switching), WP2 (Transport) and WP3 (Theory and Modelling). WP1 aims to provide reproducible and optimised switching fields in nanoscale tunneling MRAM cells compatible with energy dissipation requirements and high frequency operations. WP2 address the suppression of parasitic signal paths in read/write operations, as well as explores techniques for enhancing reproducibly signal-to-noise of the memory cell read process. WP3 will bring theoretical input for WP1 and WP2 by modelling (i) magnetic anisotropies of TRAM cells in order to reduce switching fields in small geometries and (ii) the spin-dependent tunneling characteristics of 2 and 3 terminal TRAM cells. Phase 2 tests the functionality of single cells inside the arrays as well as the novel architectures based on 2 and 3 terminal devices. This will be addressed in WP4 (Technology) including the following issues: (i) explore the limits of nanoscale lithography in the fabrication of small magnetic elements, (ii) check the TRAM performance within accepted industry standard temperature specifications, (iii) develop new strategies to handle three terminal devices. Effort must be paid on new line architectures which include a third array of lines, and on an efficient read/write process. In Phase 3, the MIMRAM and TTRAM devices are optimised with respect to cross-talk. This is addressed in WP5 (Testing and design) in which decisions are taken as to which system should be promoted in the second stage of the design. During the whole stage of this project a permanent evaluation of the progress in WP6 will insure the co-ordination of the research between the six partners (Task 6.1) as well as the achievement of the milestones and the completion of the deliverables (Task 6.2). More important, an extensive exploitation plan of the results will be produced by the industrial partners together with the coordinator of the project (Task 6.3).
Description of the work
Present lithographically defined nanoscale devices can be exponentially sensitive to atomic layer fluctuations, resulting in device specific variations that are unacceptable for manufacture. Molecular nanoelectronics has attracted considerable attention because it represents the ultimate in dimensionally scaled systems. Furthermore, molar quantities of identical devices are routinely available via chemical synthesis.
An additional incentive is the potential to utilise thermodynamically driven self-assembly of the nanoscale components. This approach eliminates any critical dimension control problems whilst forming ultradense IC arrays. Such a scheme, however, requires nanoscale electrodes and interconnects. It is this contacting problem, which has so far defeated the exploitation of molecular nanoelectronics, that will be addressed in this proposal.
The contacting scheme will incorporate a large built-in engineering redundancy, thus allowing a certain degree of fault tolerance to be exploited in design of circuit architectures. The proposed system allows direct integration and interconnection of chemically synthesised functional nanoscale components with conventional CMOS devices, offering a bolt-on technology for the fabrication of hybrid MOSFET/intramolecular circuits.
Milestones and expected results
The Saturn project is defined in order to study the growth,
the nanomanipulation as well as the electronic properties of single wall
carbon nanotubes (SWCNT) with a particular emphasis on junctions in order
to allow the use of these interesting characteristics for devices fabrication.
Therefore, the project intend to:
The project will start with the furniture of nanotubes in order to allow the work to start in the various workpackages (WP). The prospects of a future Molecular Technology-relevant technology based upon CNT are intimately linked to the success of synthetic routes aimed at the controlled production of designed devices containing selected CNT located at defined positions. This central aim of the proposed project is served on a number of different levels by the coordinated synthesis drive of WP1. Based on laser ablation technique, WP1 will provide routinely high quality material and will improve its masterage. In parallel, WP1 will investigate the possibility of in situ-localized growth using CVD technique.
This material will be used in WP2 to improve manipulation based on surface energy (self-assembly) technique. In this WP, the attachment of CNTs together or with electrodes by modification of their ends or their sidewalls will be investigated.
The work in WP3 will be devoted to the study of the electronic (transport) properties of the CNT/CNT and CNT/electrodes junctions fabricated in WP2. The improvements of the growth as well as the process will be undertaken thanks to characterizations and modelisations performed within WP4 and WP5 either on crude
CNTs or on processed tubes. In these WP experimental as well as theoretical studies will be performed to a better understanding of the electronics properties of these CNTs. Finally in WP6 some devices as room temperature transistor and single electron transistor will be fabricated to demonstrate the quality of nanotubes for Molecular Electronics, the progress realized in all the WP for a better understanding and mastery of the nanotube based technology.
Milestones and expected results
The central objective of this joint proposal is the development of DNA-based electronics. The project will focus on (i) exploring the electronic properties of DNA, (ii) using DNA as a template for other electronic molecular components, (iii) assembling DNA molecular devices, and (iv) characterizing the electrical performance of these. Single molecule electric conduction studies will provide insight into the so-far poorly understood mechanistic and dynamic issues. We will establish first prototype single-DNA-molecule electronic devices. This is a project with great scientific and technological challenges. We are confident to realize the goals however, because we have managed to bring together a consortium of the strongest european groups active in this area.
It is the goal of this proposal to understand the mechanism of charge transport in DNA, with the aim to develop an entirely novel technology for DNA electronics which exploits controlled charge migration and develops devices based on this. For this goal we will build DNA wires between electrodes, explore the conduction properties of DNA molecules and of DNA-based molecular wires, build first DNA devices, and explore the electric properties of these. The aim for the project after 3 years is to have reached an overview of the feasibility and viability of DNA-based electronics.
The consortium will design, simulate, synthesise, interconnect, assemble and test nano-devices and nano-machines starting from their atomic or molecular parts. As a nano-machine, a molecular signal processor or a computer can be fabricated in two ways:
- A very large number of "discrete" molecular gates (a molecule per gate) is interconnected on a complex network of metallic nanojunctions and wires.
- A number of gates is integrated into a single molecule, respecting quantum superposition rules, to obtain an elementary molecular-processor. These elementary processors are interconnected via a regular lattice of metallic nanowires or of optical subwavelength waveguides.
The technological objective of BUN is to evaluate these two architectures, to fabricate an example of each and to compare their relative performances. This will measure the technological success of BUN.
One scientific objective of BUN is to understand and control the electronic and mechanical intramolecular quantum behaviour of specifically designed and synthesised molecules, using a surface to localise and stabilise them. It is of prime importance to investigate and control the following properties:
- The tunnelling transport through a single molecule in a metal-molecule-metal junction with the goal to achieve a large conductance.
- The temperature-dependent and time-dependent inter and intramolecular mechanical behaviour of a single molecule on a surface.
- Electro-mechanical or electric field effects on a single molecule (the application here is to design new extrinsic grid 3-terminal gates).
- Inelastic effects in electron transport phenomena through a single molecule. These can be vibronic coupling, electron-electron interactions or screening effects (the application is here to design an intrinsic grid 3-terminal gate).
The corresponding experimental studies are supported by new software which are able to extract the detailed molecular conformation of an adsorbate from its scanning tunnelling (STM) or atomic force microscope (AFM) image, the microscopy adapted for all the phenomena to be studied in BUN.
For "discrete" molecular gates, an intermediate technological objective is to electrically interconnect molecules on a network of nanojunctions. This corresponds to the current understanding of what can be realised with molecules at the nanoscale. The important steps of the process to be developed are :
- The fabrication of the nanojunctions in an ultra-clean environment, with the development of a parallel process using the nanostencil technique.
- The assembly of the molecules at the right place using the nanostencil or a nanostamping technique. A nano-stepper is developed to pre-position those ultimately mono-molecular sources on the network.
Design software will be developed to determine fault tolerant architectures for the network and to simulate its behaviour for this discrete molecular gate approach.
The second scientific objective of BUN is to explore quantum rules for the integration of elementary functions in a single molecule. This is original to BUN and corresponds formally to the time-evolution from discrete transistors to integrated CMOS circuits. One application is the integration of a few intrinsic grid 3-terminal gates in a single molecule to perform a logic function, unless a quantum computation solution is found to be more adapted and can also be integrated (and work) in a single molecule. Those functionalized molecules will still be localised and stabilised on a wafer surface. Details objectives are:
- The understanding of long range electron tunnelling process through an atomic or a molecular wire, as opposed to the use of nanoscale wires in a ballistic transport regime.
- The design and synthesis of molecules for measurements that establish the rules governing simple serial and/or parallel electronic circuits in a single molecule.
- The optimisation of the chemical structure of an intrinsic grid 3-terminal gates.
For this integrated version of a molecular processor in a molecule, our technological objective by the end of BUN is to deposit and interconnect molecular processors on a regular lattice of nanojunctions. Important steps of the process to be developed are :
- The fabrication of a lattice of junctions in a clean environment.
- The exploration of possible optical access from the top of this lattice.
- The self-assembly technology to bring the molecular processors at the right place on the lattice.
A mapping strategy for the default processor and a dynamic procedure for reconfiguration on the lattice is proposed and simulated.